# All flip-flops,SR flipflop, D flip-flop,JK flip-flop, clocked RS flip flop Notes

In this lecture, we will discuss about all kinds of flip flops which are commonly asked in exam, there are some topics like master-slave flip-flop and other flip flop which aren’t discussed here because they are generally not found to be asked in exams(where I study). But if your require them, either you can visit youtube or ask me on comment section/fb; I will see and try to make notes of it( I have written those notes already.)

SR flip-flop

SR flip flop diagram

 S R Q Q1 1 0 1 0(set) 0 0 1 0(no change) 0 1 0 1(reset) 0 0 0 1(no change) 1 1 x x(forbidden)

What is going on the above process is that when S=1, it is giving Q=1 in first case, i.e if set=1 then Q will ON.

Likewise when Set=0 in 3rd case Q=0; as Reset(R)=1 so, it is in reset condition.

Clocked RS-Flip flop-:

Fig-: clocked RS flip flop

The table is same as SR flip flop (above). So copy and paste the above table here.

D-flip flop-:

 D clock Q Q1 1 ↑ 1 0(set) 0 ↑ 0 1(reset) – – – –

The explantion for this part is just write what you observe in table when D=1, Q=1 and set and D=0, Q=0 and reset.

This much is enough to get full marks in this topic, no need to write nonsense, after making diagrams and tables.

Next is about the JK flip flop.

JK flip-flop

There are 2 tables of JK flip flop, characteristic and excitation table.

Characteristics table-:

 Qt J (similar to S of SR) K(R) Qt+1 0 0 0 0(latch) 0 0 1 0(reset) 0 1 0 1(set) 0 1 1 1(toggle) 1 0 0 1(latch) 1 0 1 0 1 1 1 1 0 1 1 0(toggle)

Toggle-: when 0 in Qt, toggle 1 and when 1 in Qt, toggle 0; this phenomenon is called toggling in electronics.

Excitation table-:

 Qt Qt+1 J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0

In this lecture, we will discuss about all kinds of flip flops which are commonly asked in exam, there are some topics like master-slave flip-flop and other flip flop which aren’t discussed here because they are generally not found to be asked in exams(where I study). But if your require them, either you can visit youtube or ask me on comment section/fb; I will see and try to make notes of it( I have written those notes already.)

SR flip-flop

SR flip flop diagram

 S R Q Q1 1 0 1 0(set) 0 0 1 0(no change) 0 1 0 1(reset) 0 0 0 1(no change) 1 1 x x(forbidden)

What is going on the above process is that when S=1, it is giving Q=1 in first case, i.e if set=1 then Q will ON.

Likewise when Set=0 in 3rd case Q=0; as Reset(R)=1 so, it is in reset condition.

Clocked RS-Flip flop-:

Fig-: clocked RS flip flop

The table is same as SR flip flop (above). So copy and paste the above table here.

D-flip flop-:

 D clock Q Q1 1 ↑ 1 0(set) 0 ↑ 0 1(reset) – – – –

The explantion for this part is just write what you observe in table when D=1, Q=1 and set and D=0, Q=0 and reset.

This much is enough to get full marks in this topic, no need to write nonsense, after making diagrams and tables.

Next is about the JK flip flop.

JK flip-flop

There are 2 tables of JK flip flop, characteristic and excitation table.

Characteristics table-:

 Qt J (similar to S of SR) K(R) Qt+1 0 0 0 0(latch) 0 0 1 0(reset) 0 1 0 1(set) 0 1 1 1(toggle) 1 0 0 1(latch) 1 0 1 0 1 1 1 1 0 1 1 0(toggle)

Toggle-: when 0 in Qt, toggle 1 and when 1 in Qt, toggle 0; this phenomenon is called toggling in electronics.

Excitation table-:

 Qt Qt+1 J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0